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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.5k 641

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.6k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.7k 263

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.2k 364

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 912 233

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 178

Repositories

Showing 10 of 112 repositories
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 131 Apache-2.0 77 197 72 Updated Dec 12, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 351 ISC 83 46 (4 issues need help) 25 Updated Dec 12, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 41 LGPL-3.0 733 0 0 Updated Dec 12, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 41 Apache-2.0 8 17 1 Updated Dec 11, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 21 Apache-2.0 33 84 (2 issues need help) 16 Updated Dec 11, 2025
  • tac Public

    CHIPS Alliance Technical Advisory Council

    chipsalliance/tac’s past year of commit activity
    7 Apache-2.0 26 17 3 Updated Dec 11, 2025
  • caliptra-dpe Public

    High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

    chipsalliance/caliptra-dpe’s past year of commit activity
    Rust 20 Apache-2.0 28 23 10 Updated Dec 12, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 34 Apache-2.0 31 70 7 Updated Dec 11, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 307 Apache-2.0 90 28 5 Updated Dec 11, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,505 Apache-2.0 641 347 (1 issue needs help) 142 Updated Dec 11, 2025
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